use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity sample is

port (

mclk_pin :in std_logic_vector (9 downto 1);
probe_pin :buffer std_logic_vector (1 downto 0);
sysclk_pin :in std_logic

);
end sample;

architecture BEHAVIOR of sample is

component bufgs

port (

i : in std_logic;
o : buffer std_logic
);

end component;


component rstbuff

port (

mclk : in std_logic_vector (1 downto 1);
gsr : buffer std_logic;
gblreset : buffer std_logic
);

end component;


component cmp46

port (

sysclk : in std_logic;
gblreset : in std_logic;
cmp_a : in std_logic_vector (45 downto 0);
cmp_b : in std_logic_vector (45 downto 0);
probe :buffer std_logic_vector (1 downto 0)

);

end component;


component accblock

port (

a :buffer std_logic_vector (45 downto 0);
clkenb :in std_logic;
gblreset :in std_logic;
sysclk :in std_logic
);

end component;


component startup

port (

gsr : in std_logic
);

end component;


component sample_pads

port (

gblreset :in std_logic;
mclk :buffer std_logic_vector (9 downto 1);
mclk_pin :in std_logic_vector (9 downto 1);
probe :in std_logic_vector (1 downto 0);
probe_pin :buffer std_logic_vector (1 downto 0);
sysclk :buffer std_logic;
sysclk_pin :in std_logic
);

end component;


-- signals begin here

signal a : std_logic_vector (45 downto 0);
signal b : std_logic_vector (45 downto 0);
signal clkenb : std_logic_vector (1 downto 0);
signal gblreset : std_logic;
signal gsr : std_logic;
signal mclk : std_logic_vector (9 downto 1);
signal probe : std_logic_vector (1 downto 0);
signal sysclk : std_logic;




begin



sample_pads_1: sample_pads

port map (

gblreset => gblreset,
mclk (9 downto 1) => mclk (9 downto 1),
mclk_pin (9 downto 1) => mclk_pin (9 downto 1),
probe (1 downto 0) => probe (1 downto 0),
probe_pin (1 downto 0) => probe_pin (1 downto 0),
sysclk => sysclk,
sysclk_pin => sysclk_pin

);

startup_1: startup

port map (

gsr => gsr

);

accblock_1: accblock

port map (

a (45 downto 0) => a (45 downto 0),
clkenb => clkenb (0),
gblreset => gblreset,
sysclk => sysclk

);

accblock_2: accblock

port map (

a (45 downto 0) => b (45 downto 0),
clkenb => clkenb (1),
gblreset => gblreset,
sysclk => sysclk

);

cmp46_1: cmp46

port map (

sysclk => sysclk,
gblreset => gblreset,
cmp_a (45 downto 0) => a (45 downto 0),
cmp_b (45 downto 0) => b (45 downto 0),
probe (1 downto 0) => probe (1 downto 0)

);

rstbuff_1: rstbuff

port map (

mclk(1) => mclk(1),
gsr => gsr,
gblreset => gblreset

);

bufgs_1: bufgs

port map (

i => mclk (8),
o => clkenb (0)

);

bufgs_2: bufgs

port map (

i => mclk (9),
o => clkenb (1)

);

end;


library work;

configuration sample_config of sample is

for BEHAVIOR

for all: accblock use entity work.accblock(BEHAVIOR); end for;
for all: bufgs use entity work.bufgs(BEHAVIOR); end for;
for all: cmp46 use entity work.cmp46(BEHAVIOR); end for;
for all: rstbuff use entity work.rstbuff(BEHAVIOR); end for;
for all: sample_pads use entity work.sample_pads(BEHAVIOR); end for;
for all: startup use entity work.startup(BEHAVIOR); end for;

end for;

end sample_config;