rstbuff.vhd

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;


entity rstbuff is

port (

mclk : in std_logic_vector (1 downto 1);
GSR : buffer std_logic;
gblreset : buffer std_logic

);
end rstbuff ;


architecture BEHAVIOR of rstbuff is


begin

gblreset <= mclk(1);
GSR <= mclk(1);



end;

HDLMaker Generated Files
rstbuff.job Synopsys script file