rstbuff.job
TOP = rstbuff
PART = "xcv800fg680-5"
company = "IKOS Systems, Cupertino, CA"
read -format verilog rstbuff.v
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > rstbuff.fpga
report_timing > rstbuff.timing
write -format db -hierarchy -output rstbuff.db
exit