TOP = sample
PART = "4013EPQ240-3"
read -format vhdl sample.vhd

uniquify

current_design TOP
dont_touch "startup_1"
dont_touch "bufgs_1"
dont_touch "bufgs_2"
dont_touch "sample_pads_1/mclk_01_i"
dont_touch "sample_pads_1/mclk_08_i"
dont_touch "sample_pads_1/mclk_09_i"
dont_touch "sample_pads_1/probe_00_o"
dont_touch "sample_pads_1/probe_01_o"
dont_touch "sample_pads_1/sysclk_i"
remove_constraint -all
create_clock "sysclk_pin" -period 40

compile -map_effort high
disconnect_net gblreset -all

report_fpga > sample.fpga

report_timing > sample.timing

write -format db -hierarchy -output sample.db

replace_fpga

set_attribute sample "part" -type string "4013EPQ240-3"
set_attribute find(design,"*") "xnfout_write_map_symbols" -type boolean FALSE

write -format xnf -hierarchy -output sample.sxnf

ungroup -all
write_script > sample.dc
exit