sample_pads.vhd

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity sample_pads is

port (

gblreset :in std_logic;
mclk :buffer std_logic_vector (9 downto 1);
mclk_pin :in std_logic_vector (9 downto 1);
probe :in std_logic_vector (1 downto 0);
probe_pin :buffer std_logic_vector (1 downto 0);
sysclk :buffer std_logic;
sysclk_pin :in std_logic

);
end sample_pads;

architecture BEHAVIOR of sample_pads is


-- ***Components start here***
component bufgp_f

port (
i : in std_logic;
o : buffer std_logic
);

end component;


component ibuf

port (
i : in std_logic;
o : buffer std_logic
);

end component;


component ifd_f

port (
d : in std_logic;
c : in std_logic;
gblreset : in std_logic;
q : buffer std_logic
);

end component;


component ofd_f

port (
d : in std_logic;
c : in std_logic;
gblreset : in std_logic;
q : buffer std_logic
);

end component;



-- ***Signals start here***




begin



mclk_01_i: ibuf

port map (

i => mclk_pin(01),
o => mclk(01)

);

mclk_08_i: ifd_f

port map (

c => sysclk,
d => mclk_pin(08),
q => mclk(08),
gblreset => gblreset

);

mclk_09_i: ifd_f

port map (

c => sysclk,
d => mclk_pin(09),
q => mclk(09),
gblreset => gblreset

);

probe_00_o: ofd_f

port map (

c => sysclk,
d => probe(00),
q => probe_pin(00),
gblreset => gblreset

);

probe_01_o: ofd_f

port map (

c => sysclk,
d => probe(01),
q => probe_pin(01),
gblreset => gblreset

);

sysclk_i: bufgp_f

port map (

i => sysclk_pin,
o => sysclk
);

end;


library work;

configuration sample_pads_config of sample_pads is

for BEHAVIOR

for all: bufgp_f use entity work.bufgp_f(BEHAVIOR); end for;
for all: ibuf use entity work.ibuf(BEHAVIOR); end for;
for all: ifd_f use entity work.ifd_f(BEHAVIOR); end for;
for all: ofd_f use entity work.ofd_f(BEHAVIOR); end for;

end for;
end sample_pads_config;

HDLMaker Generated Files
sample_pads.job Synopsys script file