cmp46.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity cmp46 is
port (

sysclk : in std_logic;
gblreset : in std_logic;
cmp_a : in std_logic_vector (45 downto 0);
cmp_b : in std_logic_vector (45 downto 0);
probe :buffer std_logic_vector (1 downto 0)
);

end cmp46 ;


architecture BEHAVIOR of cmp46 is
signal acc :std_logic_vector (45 downto 0);
signal notequal :std_logic;

begin

cmp_p :process (sysclk,gblreset)
begin

if(gblreset = '1') then
probe <= "00";
acc <= "0000000000000000000000000000000000000000000000";
notequal <= '0';
elsif (sysclk'event and sysclk = '1') then
acc <= cmp_a - cmp_b;
if(acc = 0) then
notequal <= '0';
else
notequal <= '1';
end if;
if(notequal = '1') then
probe <= "11";
end if;
end if;

end process cmp_p;

end ;

HDLMaker Generated Files
cmp46.job Synopsys script file