bufgs.vhd



library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;

entity bufgs is

port (

i : in std_logic;
o : buffer std_logic

);
end bufgs ;


architecture BEHAVIOR of bufgs is



begin

o <= To_X01(i);



end;

HDLMaker Generated Files
bufgs.job Synopsys script file