array_pintest.top
#module "array_pintest";
#engineer "B. Joshua Rosen";
#company "Polybus Systems Corp, Westford MA";
#part_type "XCV800";
#family "virtex";
#part_number "Xilinx XCV800f680-5";
#package "fg680";
#speed "5";
#revision "1.12";
#casesensitive;
#timescale "1 ns/100 ps";
#include "array_pintest.pin";
#int i,num_bits;
#insert "BUFG.v",
connect I = half_src,
connect O = half_clk;
#insert "BUFG.v",
connect I = srcclk,
connect O = sysclk;
#insert "CLKDLL.v",
connect CLK0 = srcclk,
connect CLK180 = srcclk_l,
connect CLK270 = srclk[0],
connect CLK90 = srclk[1],
connect CLKDV = half_src,
connect CLK2X = srclk[3],
connect CLKIN = vclock,
connect CLKFB = sysclk,
connect RST = clkreset,
connect LOCKED = lock;
#insert "BUFG.v",
connect I = tclkin,
connect O = tclk;
#insert "STARTUP_VIRTEX_GSR.v", name = "?glbl",
connect GSR = greset;
#insert "rstbuff.v";
#insert "zeroone.v";
#insert "pintest_kernel.top",
connect scan_in = scan_tdi,
connect scan_enb = !scan_tms,
connect enb_special_l[0] = enb_sdram_cke_l,
connect enb_special_l[1] = enb_sdram_clk_fb_l,
connect enb_special_l[2] = enb_sdram_cs_n_l,
connect enb_special_l[3] = enb_ssram_oe_n_l,
connect enb_special_l[4] = enb_io_enable_n_l,
connect enb_special_l[5] = enb_sdram_clk_l,
connect special[0] = sdram_cke,
connect special[1] = sdram_clk_fb,
connect special[2] = sdram_cs_n,
connect special[3] = ssram_oe_n,
connect special[4] = io_enable_n,
connect special[5] = xx_sdram_clk,
connect fb_special[0] = fb_sdram_cke,
connect fb_special[1] = fb_sdram_clk_fb,
connect fb_special[2] = fb_sdram_cs_n,
connect fb_special[3] = fb_ssram_oe_n,
connect fb_special[4] = fb_io_enable_n,
connect fb_special[5] = sdram_clk,
connect fb_data[487:472] = fb_external_io[15:0],
connect data[487:472] = external_io[15:0],
connect sysclk = half_clk
;
#insert "config_scan.v",
parameter result_width = 32,
parameter done_width = 8,
connect results[31:27] = zero,
connect results[26:0] = cntr[26:0],
connect done[7:1] = zero,
connect done[0] = done;
;
#insert "assign_num.v",
parameter number = 14,
connect val[15:0] = revision[15:0];
#insert "assign_num.v",
parameter number = 0x0400,
connect val[15:0] = id[15:0];
#clock "sysclk" 25;
#clock "half_clk" 25;
#clock "tclk" 20;
#library_element "BUFG";
#library_element "CLKDLL";
#library_element "STARTUP_VIRTEX_GSR";
#fplan "clkdll_1", "dll", 2;
#fplan "bufg_1", "bufg", 2;
#fplan "bufg_2", "bufg", 3;
#fplan "bufg_3", "bufg", 0;
#maxfan 50;