config_scan.v
//-- clb_ram_16_a.v, Revision 1.0
//-- Generated by HDLMAKER Rev 5.1.7, Sunday February 13 2000
//-- Copyright (c) 2000 IKOS Systems, Cupertino, CA
//-- The information contained in this file is confidential and proprietary.
//-- Any reproduction, use or disclosure, in whole or in part, of this
//-- program, including any attempt to obtain a human-readable version of this
//-- program, without the express, prior written consent of IKOS Systems, Cupertino, CA
//-- is strictly prohibited.
//-- Engineer: B. Joshua Rosen
// The Command and Chip registers are loaded on the falling edge of scan_tms if the scan_tms
// bit has been high for at least 3 consecutive cycles.
// To load the output scan register the scan_tms bit should be asserted for 1 tclk cycle
// The start bit is pulsed for 1 cycle after the command register has been loaded
// The run bit is set by the start bit and is cleared by scan_tms
module config_scan(lock,
chip,
cmd_op,
gblreset,
revision,
id,
results,
done,
start,
run,
tclk,
scan_tdi,
scan_tms,
scan_tdo,
scan_out,
sysclk
);
// Pin Definitions
parameter result_width=32;
parameter done_width=8;
input [result_width-1:0] results;
input lock;
input [7:0] revision;
input [15:0] id;
output [15:0] chip;
reg [15:0] chip;
input [done_width-1:0] done;
input gblreset;
input tclk;
input scan_tdi;
input scan_tms;
output scan_tdo;
reg scan_tdo;
output [31:0] cmd_op;
reg [31:0] cmd_op;
output start;
reg start;
output run;
reg run;
input sysclk;
//Constants
parameter shift_len = result_width + done_width + 104;
parameter shift_msb = shift_len -1;
//Signals
reg [shift_msb:0] shift;
reg [48:0] cmd_shift;
reg [1:0] tms_cnt;
reg lock_found;
input scan_out;
// Initialize Constant Values
// Begin code body
always @(posedge sysclk or posedge start) begin
if(start) begin
lock_found <= 0;
end // if (start)
else if(lock) begin
lock_found <= 1;
end // if (lock)
end // always @ (posedge sysclk or posedge start)
always @(posedge tclk or posedge gblreset) begin
if(gblreset)
begin
shift <= 0;
cmd_shift <= 0;
chip <= 0;
cmd_op <= 0;
tms_cnt <= 0;
start <= 0;
run <= 0;
end
else
begin
if(scan_tms) begin
if(tms_cnt < 3) tms_cnt <= tms_cnt + 1;
end // if (scan_tms)
else begin
tms_cnt <= 0;
end // else: !if(scan_tms)
cmd_shift <= {scan_tdi,cmd_shift[48:1]};
if(!scan_tms && (tms_cnt == 3)) begin
chip <= cmd_shift[15:0];
cmd_op <= cmd_shift[47:16];
end // if (!scan_tms && (tms_cnt == 3))
start <= !scan_tms && (tms_cnt == 3);
if(scan_tms)
run <= 0;
else if(start)
run <= 1;
if(scan_tms) begin
shift <= {16'hFEED,
done,
results,
cmd_op,
chip,
lock_found,
id[14:0],
revision,
16'hFACE}
;
end
else begin
shift <= {scan_out,shift[shift_msb:1]};
end
end
end
always@(negedge tclk or posedge gblreset) begin
if(gblreset) begin
scan_tdo <= 0;
end // if (gblreset)
else begin
scan_tdo <= scan_tms ? cmd_shift[1] : shift[0];
end // else: !if(gblreset)
end // always@ (negedge tclk or posedge gblreset)
endmodule