config_scan.job
TOP = config_scan
PART = "xcv800fg680-5"
company = "Polybus Systems Corp, Westford MA"
read -format verilog config_scan.v
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > config_scan.fpga
report_timing > config_scan.timing
write -format db -hierarchy -output config_scan.db
exit