array_pintest.v
//-- array_pintest.v, Revision 1.12
//-- Generated by HDLMAKER Rev 5.6.5, Sunday January 21 2001
//-- Engineer: B. Joshua Rosen
//-- Copyright (c) 2001 Polybus Systems Corp, Westford MA
//-- The information contained in this file is confidential and proprietary.
//-- Any reproduction, use or disclosure, in whole or in part, of this
//-- program, including any attempt to obtain a human-readable version of this
//-- program, without the express, prior written consent of Polybus Systems Corp, Westford MA
//-- is strictly prohibited.
`timescale 1 ns/100 ps
module array_pintest(
clkreset_pin,
t_data_pin,
t_external_io_pin,
t_io_enable_n_pin,
mclock_pin,
reset_pin,
scan_tdi_pin,
scan_tdo_pin,
scan_tms_pin,
t_sdram_cke_pin,
sdram_clk_pin,
t_sdram_clk_fb_pin,
t_sdram_cs_n_pin,
t_ssram_oe_n_pin,
tclkin_pin,
vclock_pin
);
//-- IO Declarations
input clkreset_pin;
inout [471:0] t_data_pin;
inout [15:0] t_external_io_pin;
inout t_io_enable_n_pin;
input [15:3] mclock_pin;
input reset_pin;
input scan_tdi_pin;
output scan_tdo_pin;
input scan_tms_pin;
inout t_sdram_cke_pin;
input sdram_clk_pin;
inout t_sdram_clk_fb_pin;
inout t_sdram_cs_n_pin;
inout t_ssram_oe_n_pin;
input tclkin_pin;
input vclock_pin;
//-- Signal Declarations
wire [15:0] chip;
wire clkreset;
wire [31:0] cmd_op;
wire [26:0] cntr;
wire [471:0] data;
wire done;
wire [471:0] enb_data_l;
wire [15:0] enb_external_io_l;
wire enb_io_enable_n_l;
wire enb_sdram_cke_l;
wire enb_sdram_clk_fb_l;
wire enb_sdram_clk_l;
wire enb_sdram_cs_n_l;
wire enb_ssram_oe_n_l;
wire [15:0] external_io;
wire [471:0] fb_data;
wire [15:0] fb_external_io;
wire fb_io_enable_n;
wire fb_sdram_cke;
wire fb_sdram_clk_fb;
wire fb_sdram_cs_n;
wire fb_ssram_oe_n;
wire gblreset;
wire greset;
wire half_clk;
wire half_src;
wire [15:0] id;
wire io_enable_n;
wire lock;
wire [15:3] mclock;
wire one;
wire reset;
wire [15:0] revision;
wire run;
wire scan_out;
wire scan_tdi;
wire scan_tdo;
wire scan_tms;
wire sdram_cke;
wire sdram_clk;
wire sdram_clk_fb;
wire sdram_cs_n;
wire srcclk;
wire srcclk_l;
wire [3:0] srclk;
wire ssram_oe_n;
wire start;
wire sysclk;
wire tclk;
wire tclkin;
wire vclock;
wire xx_sdram_clk;
wire zero;
//-- Component Instance array_pintest_pads_1
array_pintest_pads array_pintest_pads_1
(
.clkreset_pin (clkreset_pin),
.data ({data[471:0]}),
.enb_data_l ({enb_data_l[471:0]}),
.enb_external_io_l ({enb_external_io_l[15:0]}),
.enb_io_enable_n_l (enb_io_enable_n_l),
.enb_sdram_cke_l (enb_sdram_cke_l),
.enb_sdram_clk_fb_l (enb_sdram_clk_fb_l),
.enb_sdram_cs_n_l (enb_sdram_cs_n_l),
.enb_ssram_oe_n_l (enb_ssram_oe_n_l),
.external_io ({external_io[15:0]}),
.gblreset (gblreset),
.io_enable_n (io_enable_n),
.mclock_pin ({mclock_pin[15:3]}),
.reset_pin (reset_pin),
.scan_tdi_pin (scan_tdi_pin),
.scan_tdo (scan_tdo),
.scan_tms_pin (scan_tms_pin),
.sdram_cke (sdram_cke),
.sdram_clk_pin (sdram_clk_pin),
.sdram_clk_fb (sdram_clk_fb),
.sdram_cs_n (sdram_cs_n),
.ssram_oe_n (ssram_oe_n),
.sysclk (sysclk),
.tclk (tclk),
.tclkin_pin (tclkin_pin),
.vclock_pin (vclock_pin),
.clkreset (clkreset),
.fb_data ({fb_data[471:0]}),
.fb_external_io ({fb_external_io[15:0]}),
.fb_io_enable_n (fb_io_enable_n),
.mclock ({mclock[15:3]}),
.reset (reset),
.scan_tdi (scan_tdi),
.scan_tdo_pin (scan_tdo_pin),
.scan_tms (scan_tms),
.fb_sdram_cke (fb_sdram_cke),
.sdram_clk (sdram_clk),
.fb_sdram_clk_fb (fb_sdram_clk_fb),
.fb_sdram_cs_n (fb_sdram_cs_n),
.fb_ssram_oe_n (fb_ssram_oe_n),
.tclkin (tclkin),
.vclock (vclock),
.t_data_pin ({t_data_pin[471:0]}),
.t_external_io_pin ({t_external_io_pin[15:0]}),
.t_io_enable_n_pin (t_io_enable_n_pin),
.t_sdram_cke_pin (t_sdram_cke_pin),
.t_sdram_clk_fb_pin (t_sdram_clk_fb_pin),
.t_sdram_cs_n_pin (t_sdram_cs_n_pin),
.t_ssram_oe_n_pin (t_ssram_oe_n_pin)
);
//-- Component Instance bufg_1
BUFG bufg_1
(
.I (half_src),
.O (half_clk)
);
//-- Component Instance bufg_2
BUFG bufg_2
(
.I (srcclk),
.O (sysclk)
);
//-- Component Instance clkdll_1
CLKDLL clkdll_1
(
.CLKIN (vclock),
.CLKFB (sysclk),
.RST (clkreset),
.CLK0 (srcclk),
.CLK90 (srclk[1]),
.CLK180 (srcclk_l),
.CLK270 (srclk[0]),
.CLK2X (srclk[3]),
.CLKDV (half_src),
.LOCKED (lock)
);
//-- Component Instance bufg_3
BUFG bufg_3
(
.I (tclkin),
.O (tclk)
);
//-- Component Instance glbl
STARTUP_VIRTEX_GSR glbl
(
.GSR (greset)
);
//-- Component Instance rstbuff_1
rstbuff rstbuff_1
(
.reset (reset),
.greset (greset),
.gblreset (gblreset)
);
//-- Component Instance zeroone_1
zeroone zeroone_1
(
.one (one),
.zero (zero)
);
//-- Component Instance pintest_kernel_1
pintest_kernel pintest_kernel_1
(
.chip ({chip[15:0]}),
.cmd_op ({cmd_op[31:0]}),
.fb_data ({fb_external_io[15:0],fb_data[471:0]}),
.fb_special ({sdram_clk,fb_io_enable_n,fb_ssram_oe_n,fb_sdram_cs_n,fb_sdram_clk_fb,fb_sdram_cke}),
.gblreset (gblreset),
.mclock ({mclock[15:5]}),
.scan_enb (!scan_tms),
.scan_in (scan_tdi),
.sysclk (half_clk),
.tclk (tclk),
.cntr ({cntr[26:0]}),
.data ({external_io[15:0],data[471:0]}),
.done (done),
.enb_data_l ({enb_data_l[471:0]}),
.enb_external_io_l ({enb_external_io_l[15:0]}),
.enb_special_l ({enb_sdram_clk_l,enb_io_enable_n_l,enb_ssram_oe_n_l,enb_sdram_cs_n_l,enb_sdram_clk_fb_l,enb_sdram_cke_l}),
.scan_out (scan_out),
.special ({xx_sdram_clk,io_enable_n,ssram_oe_n,sdram_cs_n,sdram_clk_fb,sdram_cke})
);
//-- Component Instance config_scan_r32d8_1 {#Parameters r32d8}
config_scan config_scan_r32d8_1
(
.results ({zero,zero,zero,zero,zero,cntr[26:0]}),
.lock (lock),
.revision ({revision[7:0]}),
.id ({id[15:0]}),
.done ({zero,zero,zero,zero,zero,zero,zero,done}),
.gblreset (gblreset),
.tclk (tclk),
.scan_tdi (scan_tdi),
.scan_tms (scan_tms),
.sysclk (sysclk),
.scan_out (scan_out),
.chip ({chip[15:0]}),
.scan_tdo (scan_tdo),
.cmd_op ({cmd_op[31:0]}),
.start (start),
.run (run)
);
defparam config_scan_r32d8_1.result_width = 32;
defparam config_scan_r32d8_1.done_width = 8;
//-- Component Instance assign_num_n14_1 {#Parameters n14}
assign_num assign_num_n14_1
(
.val ({revision[15:0]})
);
defparam assign_num_n14_1.number = 14;
//-- Component Instance assign_num_n1024_1 {#Parameters n1024}
assign_num assign_num_n1024_1
(
.val ({id[15:0]})
);
defparam assign_num_n1024_1.number = 1024;
endmodule