array_pintest.pin

#uselibrary


#pins
vclock      type = clkp,pin = d21;
tclkin      type = clkp,pin = aw19;
tclk        type = internal;
sysclk      type = internal;

clkreset        type = in,pin = e22;
scan_tms        type = in,clk = tclk,pin = at10;
scan_tdo        type = out,c2p = 7,pin = at8;
scan_tdi        type = in,p2s = 7,pin = at7;
reset           type = in,pin = e23;
mclock[15:3]        type = in,clk = sysclk,pin = [v35,u35,ac35,ab35,ar23,ar22,ar18,ac5,ab5,u5,v5,e18,e17];

ssram_oe_n      type = inout,strength=16,clk = sysclk,resistor = PULLUP,triclk = sysclk,tristate=enb_ssram_oe_n_l,pin = a27;
enb_ssram_oe_n_l    type = internal;

sdram_cs_n      type = inout,strength=16,clk = sysclk,resistor = PULLUP,triclk = sysclk,tristate=enb_sdram_cs_n_l,pin = b36;
enb_sdram_cs_n_l    type = internal;
gblreset        type = internal;

sdram_clk       type = clkp,pin = a20,p2s=7;

sdram_cke       type = inout,strength=16,clk = sysclk,resistor = PULLUP,triclk = sysclk,tristate=enb_sdram_cke_l,pin = a21;
enb_sdram_cke_l     type = internal;

io_enable_n     type = inout,strength=16,clk = sysclk,triclk = sysclk,resistor = PULLUP,tristate=enb_io_enable_n_l,pin = av4;
enb_io_enable_n_l   type = internal;

sdram_clk_fb        type = inout,strength=16,clk = sysclk,triclk = sysclk,resistor = PULLUP,tristate=enb_sdram_clk_fb_l,pin = b20;
enb_sdram_clk_fb_l  type = internal;

enb_data_l[471:0]   type = internal;
data[471:0]     type = inout,strength=16,clk=sysclk,triclk=sysclk,resistor = PULLUP,tristate=enb_data_l[471:0],pin = [d22,c22,a19,c21,b19,c19,a18,d19,b18,c18,a17,d18,b17,a16,c17,d17,b16,a15,c16,b15,d16,a14,b14,c15,a13,d15,b13,c14,a12,d14,c13,b12,d13,a11,c12,b11,c11,a10,d11,b10,c10,a9,d10,b9,c9,a8,b8,d9,a7,c8,b7,d8,a6,c7,b6,d7,a5,c6,b5,d6,a4,c5,b4,d5,e3,c2,f4,d3,f3,g4,d1,g3,e2,h4,e1,h3,f2,j4,f1,j3,g2,g1,k4,h2,k3,h1,l4,l3,j1,m3,k2,n4,k1,n3,l2,p4,p3,l1,r4,m2,r3,m1,t4,n2,n1,t3,p1,u4,r2,u3,r1,v4,t2,v3,t1,w4,u2,w3,u1,aa3,v2,aa4,v1,ab2,w2,ab3,ab4,w1,y2,ac2,y1,ac3,aa1,ac4,aa2,ab1,ad3,ac1,ad1,ad4,ae3,ae1,ae4,ae2,af3,af4,af1,ag3,af2,ag4,ag1,ah3,ag2,ah1,ah2,aj3,aj1,aj4,ak1,ak3,ak2,ak4,al1,al2,am1,al3,am2,al4,am3,an1,am4,ap1,an2,ap2,an3,ar1,an4,at1,ap3,ar2,ap4,at2,ar3,at3,ar4,au4,av5,av3,at6,au6,aw4,aw5,au7,av6,aw6,au8,at9,aw7,av8,au9,aw8,av9,au10,aw9,at11,av10,au11,aw10,au12,av11,at13,aw11,au13,at14,au14,aw12,at15,av13,au15,aw13,av14,at16,aw14,au16,av15,ar17,aw15,at17,au17,av16,aw16,at18,au18,aw17,at19,av18,au19,aw18,au21,av19,at21,at22,av20,aw20,av23,aw21,au23,av21,at23,aw22,av22,aw23,aw24,au24,aw25,at24,av25,au25,aw26,at25,av26,aw27,au26,av27,at26,aw28,au27,av28,aw29,at27,aw30,au28,av29,aw31,au29,av31,at29,aw32,au30,aw33,at30,av33,au31,at31,aw34,av32,av34,au32,aw35,at32,av35,au33,aw36,at33,au34,au36,at34,ar36,at38,ar37,ar38,ap36,at39,ap37,ar39,ap38,ap39,an36,an38,an37,an39,am36,am38,am37,al36,am39,al37,al38,ak36,al39,ak37,ak38,aj36,ak39,aj37,ah37,aj39,ah38,ah39,ag38,ag36,ag39,ag37,af39,af36,ae38,af37,af38,ae39,ae36,ae37,ad39,ad36,ac38,ac39,ad37,ab38,ab39,ac36,aa38,ac37,aa39,y38,ab36,y39,ab37,aa36,w39,aa37,w38,w37,v39,w36,u39,v38,u38,v37,t39,v36,t38,r39,u37,u36,r38,p39,t37,t36,n39,n38,r37,m39,r36,m38,p37,l39,p36,n37,l38,n36,k39,m37,k38,l37,j39,l36,k37,h39,k36,h38,j37,g39,g38,j36,f39,h37,f38,h36,e39,g37,e38,g36,d39,f37,f36,d37,e37,c38,b37,d35,c35,a36,d34,b35,c34,a35,d33,b34,c33,a34,d32,b33,c32,d31,a33,c31,b32,b31,a32,d30,a31,c30,b30,d29,a30,c29,a29,b29,b28,a28,c28,b27,d27,c27,b26,d26,c26,a26,d25,b25,c25,a25,d24,a24,b23,c24,a23,b24,b22,a22,d23,b21,c23];

enb_external_io_l[15:0] type = internal;
external_io[15:0]   type = inout,strength=16,resistor=pullup,clk=sysclk,triclk=sysclk,tristate=enb_external_io_l[15:0],pin = [d2,j2,p2,ad2,aj2,av7,av12,av17,av24,av30,av36,aj38,ad38,p38,j38,d38];

#endpins

#Summary

    Total Inputs:   20
    Total Outputs:  1
    Total Bidirects:    493
    Total Pins: 514

#endSummary


HDLMaker Generated Files
array_pintest_pads.v Verilog file
array_pintest_pads.job Synopsys script file
array_pintest.pinlist Pin list sorted by both name and number file
array_pintest.xref Pin cross reference for PC board models file
array_pintest.prj Synplicity project file
array_pintest.ucf Xilinx constraint file file