listener.v
module listener(
sysclk,
init,
fb_io,
init_val,
sample,
dump_data,
sel_parity,
load_parity,
clr_parity,
ce,
q,
d,
ram_d
);
input sysclk;
input init;
input sample;
input [1:0] dump_data;
input [1:0] fb_io;
input [1:0] init_val;
input clr_parity;
output [1:0] d;
reg [1:0] d;
output [1:0] ce;
reg [1:0] ce;
input [1:0] q;
output ram_d;
reg ram_d;
input sel_parity;
input [1:0] load_parity;
reg [5:0] state_a,state_b;
reg [1:0] sync;
reg [1:0] parity;
wire [0:31] bitstream;
assign bitstream = 32'hAA123789;
always@(posedge sysclk) begin
if(clr_parity) begin
parity <= 0;
end // if (clr_parity)
else begin
if(load_parity[0]) parity[0] <= q[0] ^ parity[0];
if(load_parity[1]) parity[1] <= q[1] ^ parity[1];
end // else: !if(clr_parity)
if(init) begin
state_a <= 0;
state_b <= 0;
ce <= 2'b11;
d <= init_val;
sync <= 0;
ram_d <= 0;
end // if (init)
else begin
sync <= fb_io;
d <= sample ? sync : q;
if((state_a[5] || (bitstream[state_a[4:0]] == sync[0])) && (state_a < 51))
state_a <= state_a +1;
else
state_a <= 0;
if((state_b[5] || (bitstream[state_b[4:0]] == sync[1])) && (state_b < 51))
state_b <= state_b +1;
else
state_b <= 0;
ce[0] <= sample ? state_a[5] : dump_data[0];
ce[1] <= sample ? state_b[5] : dump_data[1];
ram_d <= sel_parity ? (ce[0] ? ~parity[1] : ~parity[0]) : (ce[0] ? q[1] : q[0]);
end // else: !if(init)
end // always@ (posedge sysclk)
endmodule // pin_test