delay128.top
#module "delay128";
#family "virtex";
#include "delaye.pin";
#casesensitive;
#insert "zeroone.v";
#int i;
#insert "SRL16E.v",
connect Q = sh[0],
connect D = d,
connect A0 = one,
connect A1 = one,
connect A2 = one,
connect A3 = one,
connect CE = ce,
connect CLK = sysclk;
#for(i=0;i<7;i++)
{
#insert "SRL16E.v",
connect Q = sh[#i+1],
connect D = sh[#i],
connect A0 = one,
connect A1 = one,
connect A2 = one,
connect A3 = one,
connect CE = ce,
connect CLK = sysclk;
}
#insert "FDCE.v",
connect C = sysclk,
connect D = sh[#i],
connect Q = q,
connect CE = ce,
connect CLR = gblreset;
#library_element "SRL16E";
#library_element "FDCE";