delay128.job
TOP = delay128
PART = "xcv800fg680-5"
read -format verilog delay128.v
elaborate TOP
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
disconnect_net gblreset -all
report_fpga > delay128.fpga
report_timing > delay128.timing
write -format db -hierarchy -output delay128.db
replace_fpga
set_attribute delay128 "part" -type string "xcv800fg680-5"
write -format edif -hierarchy -output delay128.sedif
ungroup -all
write_script > delay128.dc
exit