top_file_format
*********************Generated Files ***************************
Hdlmaker generates the following useful files.
name.v Verilog File
name.vhd VHDL file
name_batch.Make Synopsis Make file (uses queues)
name.cmd Simulation command file
name.Make Synopsis Make file (direct dc_shell)
name.job Synopsis script
name.prj Synplicity project file
name_lf.Make Leapfrog make file
name_lf.cmd Leapfrog script
name.html HTML files
name.conn Default connection file
name.xref Pin cross reference (used when converting a PADs netlist to VHDL)
name.pinlist Pin cross reference for people to real, pins are sorted both
by name and by pin number.
name.error DRC error file, lists opens, shorts unused inputs, undriven outputs
name.rpt Report file contains loading information for all signals
name_stim.vhd Shell for a stimulus file
name_mt.do Model Tech script
name.pads PADS pcb file
name.cnet SCALD netlist
*********************how to get an example ***************************
If you want and example design type the following
hdlmaker example.top
To get a starter design type
hdlmaker starter.top
*********************.top file format ***************************
.top files have the following format
#module "file_name";
#part_type "4013E";
#package "pq240";
#speed "-3";
#directory "work";
#maxfan "16";
#include "file_name.pin";
#insert "corepath.top",connections="corepath_a.conn";
#insert "corepath.vhd",connections="corepath_b.conn";
#insert "startup.vhd";
#insert "rstbuff.vhd";
#insert "bmaoutmx.abl";
#insert "dreg12.vhd",connections="mrd.conn";
#insert "cache.top",
comment = "Cache module",
top = 10,
left = 20,
newpage = 1,
connect d[15:0] = rx[15:0],
connect q[15:0] = qx[15:0];
#insert "fdc.vhd",connections="phase_l_reg.conn";
#insert "my_entity.vhd",file="lib.vhd";
#clock "sysclk_pin" 40;
#dont_touch "startup_1";
#timespec="FROM:FFS:TO:RAMS=30";
#black_box "startup";
#black_box "fdc";
#synopsys "xnfout_constraints_per_endpoints = 0"
#locate "fdc_1","clb_r1c1";
#priority "rxvalid_l" 90;
#map_effort "high";
#syn_directive "syn_sharing" "off";
--------------------------------------------------------------------------------------
#module:
Specifies the name of the module. If no #module statement is included then the top file's
name is used, i.e. if the top file is "foo.top" then the module name will be "foo";
#module "file_name";
--------------------------------------------------------------------------------------
#part_type,#package,#speed:
Specifies the part type,package type and speed, for example:
#part_type "4013E";
#package "pq240";
#speed "-3";
#part_type "board"; Specifies a PC board, causes all of the non-IO pins to be included,
i.e. vcc, gnd, jtag, init ...
--------------------------------------------------------------------------------------
#company:
Specifies the company name for use in the copyright line inserted into generated files
#company "Polybus Systems Corp, Tyngsboro, MA";
--------------------------------------------------------------------------------------
#engineer:
Specifies the engineer's name for use in the comments inserted into the generated code
#engineer "B. Joshua Rosen";
--------------------------------------------------------------------------------------
#directory:
Specifies the VHDL working directory.
#directory "work";
--------------------------------------------------------------------------------------
#maxfan:
This is a Synplicity directive, sets the max fan out limit. The default is a soft limit of 100.
To set a soft fan out limit do the following:
#maxfan 16;
If a hard limit is desired add the word "hard" to the line;
#maxfan 25 hard;
--------------------------------------------------------------------------------------
#synplicity:
This is a Synplicity directive, places the quoted string into the synplicity project file
#synplicity "set_option -default_enum_encoding onehot";
--------------------------------------------------------------------------------------
#include
Directly includes the text of the file. If the file is a .pin file then the pad ring and
entity declarations are automaticcaly generated. An #include of a pin file is required.
#include "file_name.pin";
--------------------------------------------------------------------------------------
#insert,#insert_upcase:
Insert an instance of a component. The extension specifies the source type. insert_upcase is similiar to
insert except that in verilog synthesys mode the component name is upper cased.
#insert "foo.top"; Generates a VHDL file from the .top file and inserts it.
#insert "foo.vhd"; Insert a vhdl file.
#insert "foo.abl"; Executes ABEL, converts the results to VHDL and then inserts it.
The default signal name that is attached to a pin has the same name as the pin.
If a different name is required this can be accomplished with a connection file.
#insert "corepath.top",connections="corepath_a.conn";
The format for a connection file is shown below:
#connect d[11..0] = input_bus[11..0];
#connect gblreset = gblreset;
#connect q[11..0] = reg_results[11..0];
#connect sysclk = sysclk;
#connect q_l[11..0] = #a[#high:#high - 11];
#parameter width = 16;
The # character (except for the keywords #connect or #parameter) is used to indicate an evalatable expression.
In the example above #a specifies a string variable for the bus name, while #high:#high-11 specifies
a 12 bit range where the msb is determined by the integer varaible #high;
A default .conn file is automatically generated for each component called by a
.top file. The simple way to make a .conn file is to run hdlmaker once and then
edit the resulting .conn files.
Connections may also be made in the .top file by using the connect statement,
#insert "foo.v",
connect d[12:0] = ibus[12:0],
connect enb = enable;
The format of the connect statement is identical to the .conn file except that the keyword is connect,
not #connect.
For cnet files, parts may be substituted by using the part command,
#insert "my_board.cnet",
part U10 = ttl74374.v,
part U15 = ctrl_xilinx.top,
part U[3:8] = sram16x32.v;
The default for a netlist file is the .v or .vhd file that corresponds to the component name in the netlist.
Multiple instances of a component may be specified with a single statement,as shown above for srams U3-U8.
The default instance name is the file name plus the instance number, for example
#insert "foo.v"; is foo_1
#insert "foo.v"; is foo_2
#insert "bar.v"; is bar_1
#insert "foo.v"; is foo_2
You may define an instance name as follows:
#insert "foo.v",name = "u"; is u1
#insert "foo.v",name = "u"; is u2
#insert "bar.v",name = "u"; is u3
#insert "foo.v",name = "u"; is u4
The default source file is the same as the entity/module name. An alternate source file name
may be specified with a file = statement,
#insert "ent.vhd",file="lib.vhd";
A single comment may be added with the comment command.
#insert "foo.v",
comment = "This is foo";
Placement commands may be passed to the schematic generator with the top, left and newpage commands.
#insert "ttl74fct374.v",
newpage = 1,
top = 10,
left = 20;
Where any non zero argument to newpage forces the schematic generator to start a new page, and left and top
are in .1 inch units
--------------------------------------------------------------------------------------
#insert_script Inserts the component into all relevant scripts and make files
(like #insert) but does not instantiate it
#insert_script "foo.vhd";
--------------------------------------------------------------------------------------
#add_package Adds packages to the Synopsys job file, Synplicity project and the verilog script
#add_package "my_package.vhd";
#add_package "my_library.v";
--------------------------------------------------------------------------------------
#clock
#clock tells Synopsis that a particular signal is a clock. The example below
specifies that sysclk_pin is a 40 ns clock. The _pin at the name is there because
hdlmaker names all external pin signals name_pin. For Synplicity #clock is used to
set the frequency. Frequency is set to 1000/#clock (for example: #clock 40 sets the
Synplicity frequency value to 25);
#clock "sysclk_pin" 40;
--------------------------------------------------------------------------------------
#ignore
#ignore Tells the Xiling tools to ignore any time specs associated with a net.
#ignore "my_net";
--------------------------------------------------------------------------------------
#dont_touch
This is a Synopsis directive that tells it not to remove a component even though it's
outputs aren't connected. A dont_touch is required for the startup (reset) block. It is
also required for IO buffers. However hdlmaker takes care of IO buffers itself so you don't
have to do anything for those.
#dont_touch "startup_1";
--------------------------------------------------------------------------------------
#timespec,#timegrp
These are Xilinx timespec directives. The example shown below specifies that the
clock to RAM setup is 30 ns.
#timespec="FROM:FFS:TO:RAMS=30";
Time specs may also use expressions , the syntax for is:
#timespec from_expression,to_expression,time_expression,priority_expression (optional);
example:
#timespec "foo_a" + i, "bar_a" + j, k, l;
where i,j,k and l are variables.
example:
#timespec foo, "FFS", 20, 1;
In this example only foo is a variable, "FFS" is the Xilinx name for all flipflops, 20 and 1,
mean 20 ns and priority 1;
--------------------------------------------------------------------------------------
#tnm_net,#tnm_inst,#tnm_pin
These are Xilinx timing name directives. The example shown groups together all signals
named areg* (areg_0,areg_1...) in the datapath_1 module. This is used in conjucntion with the
#timespec directive.
#tnm_net "areg" "datapath_1/areg*";
places the following into the ucf
NET "datapath_1/areg*" TNM="areg";
Expressions may be used as follows:
#tnm_net path_name_expression, path_expression;
#tnm_inst path_name_expression, path_expression;
#tnm_pin path_name_expression, path_expression;
example:
#tnm_inst "tms_iff", "obuft_" $ name $ "_pads_1/scan_tms_iff" ;
where name is a variable.
--------------------------------------------------------------------------------------
#no_timespecs
Stop Synopsys from emitting time specs in the SXNF files. #no_timespecs is the same as
#synopsys "xnfout_constraints_per_endpoint = 0"
--------------------------------------------------------------------------------------
#input_setup
Specify an input setup constraint to Synopsys
#input_setup "pin_name" "clock_name" 20;
This is equivalent to:
#synopsys "set_input_delay -clock clock_name -max 20 pin_name";
--------------------------------------------------------------------------------------
#input_hold
Specify an input hold constraint to Synopsys
#input_hold "pin_name" "clock_name" 20;
This is equivalent to:
#synopsys "set_input_delay -clock clock_name -min 20 pin_name";
--------------------------------------------------------------------------------------
#black_box
This is a Synplicity directive. It is similiar to the Synopsys #dont_touch command.
Hdlmaker also uses the black_box directive to exclude modules from Synopsys Make
files.
#black_box "startup";
--------------------------------------------------------------------------------------
#state_machine
Sets the Synplicity FSM compiler switch on.
--------------------------------------------------------------------------------------
#resource_sharing_off
Sets the Synplicity resource sharing switch off, the default is on
--------------------------------------------------------------------------------------
#pipe_off
Sets the Synplicity resource pipe switch off, the default is on
--------------------------------------------------------------------------------------
#write_verilog,#write_vhdl
Sets the write verilog or vhdl option in Synplicity
--------------------------------------------------------------------------------------
#pullup,#pulldown
Inserts pull up and pull down resistors and marks them with dont_touche and black_box attributes
#pullup "pull_high";
#pulldown "pull_low";
--------------------------------------------------------------------------------------
#boundary_optimization
Enables some logic optimization across hierarchical boundaries. #flatten takes precedence
over #boundary_optimization.
--------------------------------------------------------------------------------------
#flatten
Forces Synopsys to flatten the design
--------------------------------------------------------------------------------------
#synopsys
This allows you to add arbitrary commands to the Synopsys .job file
#synopsys "xnfout_constraints_per_endpoints = 0"
--------------------------------------------------------------------------------------
#syn_directive
Add synthesys directives to the module or entity. For example the Synplicity directive syn_sharing
#syn_directive "syn_sharing" "off";
Will produce the following results in Verilog and VHDL
//verilog
module dreg(
d,
q,
sysclk
) /* syn_sharing = "off" */ ;
//-- IO Declarations
input [7:0] d;
output [7:0] q;
input sysclk;
--vhdl
entity dreg is
port (
d :in std_logic_vector (7 downto 0);
q :buffer std_logic_vector (7 downto 0);
sysclk :in std_logic
);
end dreg;
architecture BEHAVIOR of dreg is
attribute syn_sharing of behavior : architecture is "off";
--------------------------------------------------------------------------------------
#buffer
Specify the type of output used for VHDL
#buffer "out";
#buffer "inout";
#buffer "buffer"; -- this is the default
--------------------------------------------------------------------------------------
#locate
Insert placement constraints into the appropriate constraint file (.cst file for the
old ppr Xilinx tool, .pcf file for the new Xilinx place and route tool).
#locate "fdc_1","clb_r1c1";
--------------------------------------------------------------------------------------
#priority
Insert a prioritize command to PAR into the pcf file. Prioritize is used to up the
priority of a signal to the place and route software.
#priority "rxvalid" 90;
Valid priority levels run from 1 to 99 (highest priority). The default priority is 3.
--------------------------------------------------------------------------------------
#timescale
Insert Verilog `timescale command
#timescale "1 ns/1 ps";
Inserts the following
`timescale 1 ns/1 ps
--------------------------------------------------------------------------------------
#place
Insert Xilinx placement constraints in the .ucf and .pcf files
#place "crc_blk_shft2_1/crc72x4_1/y_reg" from 0 to 12 step 2 row 1 step 0 col 1 step 2 rsrc ffx;
#place "crc_blk_shft2_1/crc72x4_2/y_reg" from 1 to 30 step 1 row 1 step 1/2 col 1 step 0 rsrc ffx;
where
from # Starting bit number, in the example above this would be crc_blk_shft2_1/crc72x4_1/y_reg<0> (default 1)
to # Ending bit number, in the example above this would be crc_blk_shft2_1/crc72x4_1/y_reg<31> (default 1)
step # Stride, applies to the previous parameters (default 1)
row # Starting row (default 1)
col # Starting col (default 1)
rsrc %s Resource type, specifies the particular resource for example ffx, ffy (default none).
Numbers (#) may be defined as simple integers, ratios or products, the following are all legal
2
1/2
3*2
2*3/2
--------------------------------------------------------------------------------------
#uselib
Insert Verilog uselib command
#uselib "/tools/xilinx/xact-5.2.1-verilog/verilog4000e";
Inserts the following
`uselib dir=/tools/xilinx/xact-5.2.1-verilog/verilog4000e libext=.v
--------------------------------------------------------------------------------------
#casesensitive
Allow case sensitive Verilog code, the default is to downcase everything. The env variable
HDLMAKER_ALLOW_CASE_SENSTIVE can also be used.
--------------------------------------------------------------------------------------
#allowtrailingnumbers
Allow bus names to end in a number, the default is to append _bus to any bus name that ends
in a number. The env variable HDLMAKER_ALLOW_TRAILING_NUM also can be used.
--------------------------------------------------------------------------------------
#use_defparam
Hdlmaker can pass parameters to a Verilog module using either defparam or by passing them as ordered
arguments. The default is defparam, to use the argument syntax do
#use_defparam 0
or use the HDLMAKER_USE_DEFPARAM env variable.
Examples:
#use_defparam 1;
#insert "srfifo_ctrl.v",
#parameter WIDTH = 32;
Generates:
srfifo_ctrl srfifo_ctrl_w32_1
(
);
defparam srfifo_ctrl_w32_1.WIDTH = 32;
#use_defparam 0;
#insert "srfifo_ctrl.v",
#parameter WIDTH = 32;
Will generate
srfifo_ctrl #(32) srfifo_ctrl_w32_1
(
);
--------------------------------------------------------------------------------------
Environment variables:
In your .cshrc you must specify four environment variables.
HDLMAKER_LIB Specifies the path to hdlmaker's library
HDLMAKER_MACHINE Specifies the Machine used for the synthesis batch queue
If there is no batch queue then either don't set this
variable or set it to 0
HDLMAKER_FAMILY Specifies the FPGA family, legal values are
xc4000e
xc4000ex
xc5200
orca2ca
HDLMAKER_SYNTHESYS Specifies the synthesys tool, legal values are
synopsys
synplicity
fpgaexpress
exemplar
rtlc
HDLMAKER_SIMULATOR Specifies the simulation tool, legal values are
leapfrog
verilogxl
modeltech
HDLMAKER_BATCH_Q Specifies the synthesys batch queue script name. If there is
no batch queue then set this variable to the systhesis program name.
For example if you are running synopsys use:
setenv HDLMAKER_BATCH_Q {"dc_shell - f"}
HDLMAKER_SYNTHESYS_EXTENSION Specifies the file extension of the command script. For the
batch system this variable may be left undefined or set to 0. If
dc_shell is being used this variable must be set to .job.
setenv HDLMAKER_SYNTHESYS_EXTENSION {.job}
HDLMAKER_LANGUAGE Specifies hdlmaker's output language, the default is VHDL.
setenv HDLMAKER_LANGUAGE verilog
setenv HDLMAKER_LANGUAGE vhdl
HDLMAKER_VERILOG_CMD Specifies the verilog command used in the verilog script.
setenv HDLMAKER_VERILOG_CMD "virsim verilog-vw"
HDLMAKER_COMPANY Default company name (can be overriden by the #company statement in the top file)
Used for copyright comments added to the code
setenv HDLMAKER_COMPANY "Polybus Systems, Inc. Tyngsboro, MA."
HDLMAKER_ENGINEER Default engineer's name (can be overriden by the #engineer statement in the top file)
If defined the engineer's name will be included in a comment line at the top
of all generated code.
setenv HDLMAKER_ENGINEER "B. Joshua Rosen"
HDLMAKER_CASE_SENSITIVE Allow case sensitive Verilog code, the default is to downcase everything.
setenv HDLMAKER_CASE_SENSITIVE TRUE
HDLMAKER_ALLOW_TRAILING_NUM Allow bus names to end in a number, the default is append _bus to
any bus name that ends in a number.
setenv HDLMAKER_ALLOW_TRAILING_NUM TRUE
setenv HDLMAKER_LIB {/usr/local/lib/hdlmaker}
setenv HDLMAKER_MACHINE {goffin}
setenv HDLMAKER_FAMILY {xc4000e}
setenv HDLMAKER_SYNTHESYS {synplicity}
setenv HDLMAKER_BATCH_Q {s3fpga2job_q}
setenv HDLMAKER_USE_DEFPARAM {0,1} Enable or disable the use of defparams in Verilog,
The default is to use defparam
________________________________________________________________________
ABEL Conversions
Hdlmaker converts ABEL to VHDL by translating the .eqn and .tt1 output files
from ABEL. The script hdlmaker_lib/csh/runabl is used by hdlmaker to invoke ABEL.
This script must be modified for your environment. This script does the following:
runs ABEL
copies the .eqn and .tt1 result files into the local directory
If the ABEL source file has pin numbers then an .xref file will automatically
be generated. PADs netlists that include ABEL based PLDs will be converted into
VHDL. An attribute called "pldfile" which references the .abl file must be attached
to each PLD.
________________________________________________________________________
Loop language and variables
Hdlmaker supports a C like language which can be used to generate code with. There
are two variable types
#int 32 bit integers
#string 32 byte radix 36 strings
examples
#int foo,bar,my_array[2][3];
#string a_str,b_str,c_str[2];
Variables may be declared as either scalers or arrays.
The strings are radix 36 plus the special character _. String arithmetic values characters as follows:
Character Value
0:9 0:9
a:z 10:35
_ Special case, _ op anything is _
For example
"foo_a" + 1 is equal to "foo_b"
"foo_a" + "1" is also equal to "foo_b"
The operations supported are
+
-
* integers only
/ integers only
++
--
|
&
^
~
!
<< Left shift (integers only)
>> Right shift (integers only)
<> Rotate (integers only)
$ Concatenate (strings only)
Assignment operators are
=
+=
-=
*=
/=
<<=
>>=
<>=
$=
Comparison operators are
==
!=
<=
>=
>
<
#assign Assignment command
#assign foo = a + b * c;
#assign bar += foo << 1;
#for For loops, same syntax as C, the loop must be designated with {}
#for(i=0;i < x + y;i++)
{
}
#if If/else is the same as C, except that {} must be used
#if(a < b)
{
#assign i=i+1;
#insert "dreg8.v",connections="reg.conn";
}
#else
{
#insert "mux2x4.v",connections="mux.conn";
}
#while While condition is true, requires {}
#while(a < b)
{
#insert "dreg8.v",connections="reg.conn";
#assign a++;
}
The variables are passed through to the connection file evaluator.
#fplan Floor plan command
fplan inserts a constraint in the the ucf or pcf (if the -pcf switch is on) file.
The default location constraint is for CLBs. DLLs, BUFGs and block RAMs may be
placed by using the words dll, bufg, ramb4 in place of the row number. Area
constraints may be specified by using the keyword area.
#fplan component_name_string, row, col;
#fplan dll_1, "dll", 1;
#fplan bufg_2, "bufg", 3;
#fplan "dcache_1/ramb4_s8_s16_8", "ramb4",0,1;
For VirtexE the DLL locations 0S,0P...3S,3P. To specify a VirtexE location place the
location in quotes:
#fplan "clkdll_1", "dll", "2P";
Area constraints are done as follows:
#fplan "path", "area", top, left, bottom, right;
#fplan "icache_1/ram16x18_1", "area", 1, 7, 9, 7;
#int row,col,i,j,k,firstrow,lastrow,probe,firstcol,lastcol;
#string qx,cmp_a,cmp_b,diff,xdiff;
#assign i = 1;
#assign firstrow = 1;
#assign lastrow = 36;
#assign cmp_a = "x_a";
#assign cmp_b = "x_b";
#assign diff = "diff_a";
#assign xdiff = "diff_b";
#assign firstcol = 1;
#for(k=0;k<2;k++)
{
#assign probe = k << 1;
#assign j = 0;
#assign lastcol = firstcol + 17;
#assign qx = "x_a" + k;
#for(row=firstrow;row<= lastrow;row +=2)
{
#for(col=firstcol;col<=lastcol;col++)
{
#insert "reg_xor9.v",connections="reg_xor.conn";
#fplan "reg_xor9_" $ i $ "_qx",row,col;
#assign i++;
#assign j++;
}
}
#insert "src_cntr.v",connections="src_cnt.conn";
#insert "error_compare4.v",connections="err_cmp.conn";
#assign firstcol = lastcol + 1;
#assign cmp_a = "x_b";
#assign cmp_b = "x_a";
#assign diff = "diff_b";
#assign xdiff = "diff_a";
}