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accblock.top

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#module "accblock";
#part_type "4013E";
#family "XC4000";
#package "PQ240";
#speed "-3";

#directory "work";
#include "accblock.pin";
#insert "acc46.vhd",connections="acca.conn";
#insert "acc46.vhd",connections="accb.conn";
#insert "acc46.vhd",connections="accc.conn";
#insert "acc46.vhd",connections="accd.conn";
#insert "acc46.vhd",connections="acce.conn";
#insert "acc46.vhd",connections="accf.conn";
#insert "acc46.vhd",connections="accg.conn";
#insert "acc46.vhd",connections="acch.conn";
#insert "acc46.vhd",connections="acci.conn";
#insert "acc46.vhd",connections="accj.conn";
#insert "acc46.vhd",connections="acck.conn";

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HDLMaker Generated Files

accblock.vhd	VHDL file
accblock.job	Synopsys script file
accblock.cst	Xilinx constraint file
accblock.prf	ORCA constraint file
accblock.pcf	Xilinx M1 constraint file
accblock.ucf	Xilinx M1 constraint file
accblock.prj	Synplicity Project file
accblock.Make	Synopsy Make file
accblock_lf.Make	Leapfrog Make file
accblock_mt.cmd	Model Tech script file
accblock_batch.Make	Synopsis batch Make file
accblock.errors	DRC Error file

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