acc46.vhd

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity acc46 is
port (

clkenb : in std_logic;
sysclk : in std_logic;
gblreset : in std_logic;
a : in std_logic_vector (45 downto 0);
b : in std_logic_vector (45 downto 0);
y : buffer std_logic_vector (45 downto 0)
);

end acc46 ;


architecture BEHAVIOR of acc46 is

constant ivalue :std_logic_vector (63 downto 0) := TO_X01(X"0145456789ABCDEF");

begin

acc_p :process (sysclk,clkenb,gblreset)
begin

if(gblreset = '1') then
y <= ivalue(45 downto 0);
elsif (sysclk'event and sysclk = '1') then
if(clkenb = '1') then
y <= a + b;
end if;
end if;

end process acc_p;

end ;

HDLMaker Generated Files
acc46.job Synopsys script file