Xilinx Test Patterns

<body topmargin=0 leftmargin=0 marginheight=0 marginwidth=0> <table cellpadding=0 cellspacing=0 border=0><tr> <td valign="top" colspan=2 height=90 BGCOLOR="#CC9900" TEXT="#080000" bgproperties="fixed" background="045005a0dwnjzk.gif"> <div> <B>Xilinx Test Patterns</B></div> <bR> <div> </div> </td> </tr><tr> <td valign="top" width=210 BGCOLOR="#FFFFFF" TEXT="#080000"> <bR> <div> <A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B><IMG SRC="03f69830.gif" border=0 width="105" height="131" ALIGN="BOTTOM" HSPACE="0" VSPACE="0"></B></U></A></div> <div> <A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B>Polybus Systems Corp</B></U></A></div> <div> <B>23 Providence Rd</B></div> <div> <B>Westford, MA 01886</B></div> <div> <B>(978)828-0944</B></div> <div> <A HREF="mailto:bjrosen@polybus.com" TARGET="_top" TITLE="mailto:bjrosen@polybus.com"><U><B>bjrosen@polybus.com</B></U></A></div> <bR> <div> <A HREF="index_m.htm#overview" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>Overview</B></U></A></div> <div> <A HREF="index_m.htm#why_do_in_system_testing_" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>Why Do In System Testing?</B></U></A></div> <div> <A HREF="index_m.htm#how_effective_are_the_polybus_fpga_test" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>How Effective Are The Polybus FPGA Test</B></U></A></div> <div> <A HREF="index_m.htm#how_common_are_fpga_defects_" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>How Common Are FPGA Defects?</B></U></A></div> <div> <A HREF="index_m.htm#how_serious_are_fpga_defects_" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>How Serious Are FPGA Defects?</B></U></A></div> <div> <A HREF="index_m.htm#what_type_of_system_needs_in_system" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>What Type Of System Needs In System</B></U></A></div> <div> <A HREF="index_m.htm#interface_requirements" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>Interface Requirements</B></U></A></div> <div> <A HREF="index_m.htm#what_sort_of_customization_is_available_" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>What Sort of Customization Is Available?</B></U></A></div> <div> <A HREF="index_m.htm#test_coverage" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>Test Coverage</B></U></A></div> <div> <A HREF="index_m.htm#further_information" TARGET="TRLX_Middle" TITLE="Xilinx Test Patterns"><U><B>Further Information</B></U></A></div> </td> <td valign="top" height=390 BGCOLOR="#FFFFFF" TEXT="#080000"> <bR> <div> <B> <A NAME="overview"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Overview</B></div> <div> Polybus Systems offers a customizable set of FPGA test patterns for all Xilinx FPGAs. The suite consists of over 400 patterns which test the internal functionality and interconnect of any Xilinx FPGA. The tests help eliminate FPGAs that have failed due to handling problems and infant mortality. In addition the patterns provided a greatly enhanced level of testing which helps assure the future upgradability of FPGA based systems.</div> <bR> <div> The test patterns may be run in system or on a chip tester to provide a greater level of screening.</div> <bR> <div> <B> <A NAME="why_do_in_system_testing_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Why Do In System Testing?</B></div> <div> In system testing can provide a much higher level of coverage then manufacturer screening. Manufacturer tests, run on a chip tester, are limited to a handful of patterns and a total test time that can be a few seconds at most. In system tests have no such limitations. The Polybus test suite consists of over 400 patterns and the test time can be anywhere from five minutes to many hours (when used for system burn in). </div> <bR> <div> <B> <A NAME="how_effective_are_the_polybus_fpga_test"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>How Effective Are The Polybus FPGA Test Patterns?</B></div> <div> FPGAs present a unique testing problem. FPGAs have hugely complicated interconnect networks that can be connected in a nearly infinite number of ways. As such it is theoretically impossible to test every possible pathway. Manufacturer's tests attempt to test each individual switch but they can't test every interconnect path. Testing every switch will eliminate parts with major defects but it can't find every problem. Polybus' test suite has been designed to test a much wider range of interconnect patterns. While Polybus can not claim that it's test suite can provide 100% coverage, as stated earlier that's theoretically impossible, customer experience has shown that in system testing with Polybus' test patterns can reduce the probability of shipping a defective part by up to two orders of magnitude.</div> <bR> <div> <B> <A NAME="how_common_are_fpga_defects_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>How Common Are FPGA Defects?</B></div> <div> Polybus has produced in system test patterns for seven generations of Xilinx FPGAs. Over that time the FPGA defect rate has been fairly constant, ranging between 1% and 3%.</div> <bR> <div> <B> <A NAME="how_serious_are_fpga_defects_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>How Serious Are FPGA Defects?</B></div> <div> Defects are typically small, generally effecting about one in fifty patterns, that is if fifty different patterns are loaded into the defective FPGA forty nine will work correctly and one will work incorrectly. For a system that consists of a single FPGA and a single programming pattern the probability of a FPGA caused failure is small, typically between 1 in 2500 and 1 in 10000 systems. For systems with a single dynamically loaded FPGA the probability of an FPGA caused failure approaches 1 in 50 as the number of different programming patterns is increased. For systems with large numbers of FPGAs the probability of a FPGA caused failure also increases.</div> <bR> <div> <B> <A NAME="what_type_of_system_needs_in_system"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>What Type Of System Needs In System FPGA Testing?</B></div> <div> Any system that supports field upgradable FPGA pattern's benefits tremendously if the FPGAs are tested with Polybus' in system test patterns. Every time the FPGA pattern is changed you run the risk that the new pattern won't work even though the FPGA worked perfectly with the old pattern. Supplemental screening with Polybus' test patterns significantly reduce the risk that a field upgrade will cause a previously working system to stop functioning.</div> <bR> <div> Any system where maximum reliability is required can also benefit from the Polybus FPGA test suite. Even systems where in circuit testing is impossible, i.e. serial prom based systems, can benefit by doing an additional prescreen on a chip tester.</div> <bR> <div> <B> <A NAME="interface_requirements"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Interface Requirements</B></div> <div> The interface is customized for the target system. Interface requirements are simple, consisting of a reset, a run signal, a done signal and an error signal. The interface can use a few dedicated pins, a JTAG scan chain, or a custom scan chain as determined by the needs of the target system. In addition to in system tests the Polybus Test Patterns have also been used on chip testers to provide a higher level of prescreening then the standard Xilinx test patterns alone.</div> <bR> <div> <B> <A NAME="what_sort_of_customization_is_available_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>What Sort of Customization Is Available?</B></div> <div> Polybus is prepared to provide any sort of interface that the system designer may require. Customization may be as simple as a custom pinout or as complicated as a user defined scan chain. In addition, Polybus can provide in system IO tests in addition to the standard suite of internal tests.  By their very nature IO tests are system specific and as such must be customized for each system.</div> <bR> <div> <B> <A NAME="test_coverage"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Test Coverage</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">LUT RAM</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Block RAM</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Tristate Buffers</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">DLLs, DCMs</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">DFLOPs</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Latches</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">LUT Logic</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">F5 Mux</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">F6 Mux</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">F7 an F8 Muxes (Virtex2 only)</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Carry Logic</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Longline</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Multipliers (Virtex2 Only)</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Shift Registers</B></div> <div> <B><IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Extensive Interconnect Coverage (North,South,East,West,NE,NW,SE,SW, multiple strides)</B></div> <bR> <div> <B> <A NAME="further_information"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Further Information</B></div> <div> For further information and pricing please contact</div> <bR> <div> Joshua Rosen <A HREF="mailto:bjrosen@polybus.com" TARGET="_top" TITLE="mailto:bjrosen@polybus.com"><U>bjrosen@Polybus.com</U></A></div> <div> 978 828-0944</div> <bR> <bR> <bR> <bR> <bR> </td> </tr></table></body>