sample_pads.vhd
--// sample_pads.vhd
--// Generated by HDLMAKER Rev 5.6.0, Thursday January 11 2001
--// Copyright (c) 2001 Polybus Systems Corp, Inc., Westford, MA
--// The information contained in this file is confidential and proprietary.
--// Any reproduction, use or disclosure, in whole or in part, of this
--// program, including any attempt to obtain a human-readable version of this
--// program, without the express, prior written consent of Polybus Systems Corp, Inc., Westford, MA
--// is strictly prohibited.
--// Engineer: B. Joshua Rosen
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity sample_pads is
port (
gblreset :in std_logic;
mclk :buffer std_logic_vector (9 downto 8);
mclk_pin :in std_logic_vector (9 downto 8);
probe :in std_logic_vector (1 downto 0);
probe_pin :buffer std_logic_vector (1 downto 0);
reset :buffer std_logic;
reset_pin :in std_logic;
sysclk :buffer std_logic;
sysclk_pin :in std_logic
);
end sample_pads;
architecture BEHAVIOR of sample_pads is
--// ***Components start here***
component fdc
port (
d : in std_logic;
c : in std_logic;
clr : in std_logic;
q : buffer std_logic
);
end component;
component ifd_f
port (
d : in std_logic;
c : in std_logic;
q : buffer std_logic
);
end component;
--// ***Signals start here***
signal probe_000_out : std_logic;
signal probe_001_out : std_logic;
begin
mclk_008_i: ifd_f
port map (
c => sysclk,
d => mclk_pin(008),
q => mclk(008)
);
mclk_009_i: ifd_f
port map (
c => sysclk,
d => mclk_pin(009),
q => mclk(009)
);
probe_000_o: OBUF_F
port map (
I => probe_000_out,
O => probe_pin(000)
);
probe_000_off: fdc
port map (
c => sysclk,
d => probe(000),
q => probe_000_out,
clr => gblreset
);
probe_001_o: OBUF_F
port map (
I => probe_001_out,
O => probe_pin(001)
);
probe_001_off: fdc
port map (
c => sysclk,
d => probe(001),
q => probe_001_out,
clr => gblreset
);
reset_i: IBUF
port map (
I => reset_pin,
O => reset
);
sysclk_i: BUFGP
port map (
I => sysclk_pin,
O => sysclk
);
end;