accblock.vhd
--// accblock.vhd
--// Generated by HDLMAKER Rev 5.6.0, Thursday January 11 2001
--// Copyright (c) 2001 Polybus Systems Corp, Inc., Westford, MA
--// The information contained in this file is confidential and proprietary.
--// Any reproduction, use or disclosure, in whole or in part, of this
--// program, including any attempt to obtain a human-readable version of this
--// program, without the express, prior written consent of Polybus Systems Corp, Inc., Westford, MA
--// is strictly prohibited.
--// Engineer: B. Joshua Rosen
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity accblock is
port (
a_pin :buffer std_logic_vector (45 downto 0);
clkenb_pin :in std_logic;
gblreset_pin :in std_logic;
sysclk_pin :in std_logic
);
end accblock;
architecture BEHAVIOR of accblock is
component acc46
port (
clkenb : in std_logic;
sysclk : in std_logic;
gblreset : in std_logic;
a : in std_logic_vector (45 downto 0);
b : in std_logic_vector (45 downto 0);
y : buffer std_logic_vector (45 downto 0)
);
end component;
--// signals begin here
signal a : std_logic_vector (45 downto 0);
signal b : std_logic_vector (45 downto 0);
signal c : std_logic_vector (45 downto 0);
signal clkenb : std_logic;
signal d : std_logic_vector (45 downto 0);
signal e : std_logic_vector (45 downto 0);
signal f : std_logic_vector (45 downto 0);
signal g : std_logic_vector (45 downto 0);
signal gblreset : std_logic;
signal h : std_logic_vector (45 downto 0);
signal i : std_logic_vector (45 downto 0);
signal j : std_logic_vector (45 downto 0);
signal k : std_logic_vector (45 downto 0);
signal sysclk : std_logic;
begin
acc46_1: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => b (45 downto 0),
b (45 downto 0) => e (45 downto 0),
y (45 downto 0) => a (45 downto 0)
);
acc46_2: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => a (45 downto 0),
b (45 downto 0) => c (45 downto 0),
y (45 downto 1) => b (44 downto 0),
y(0) => b(45)
);
acc46_3: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => b (45 downto 0),
b (45 downto 0) => d (45 downto 0),
y (45 downto 2) => c (43 downto 0),
y (1 downto 0) => c (45 downto 44)
);
acc46_4: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => c (45 downto 0),
b (45 downto 0) => e (45 downto 0),
y (45 downto 3) => d (42 downto 0),
y (2 downto 0) => d (45 downto 43)
);
acc46_5: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => d (45 downto 0),
b (45 downto 0) => f (45 downto 0),
y (45 downto 4) => e (41 downto 0),
y (3 downto 0) => e (45 downto 42)
);
acc46_6: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => e (45 downto 0),
b (45 downto 0) => g (45 downto 0),
y (45 downto 3) => f (42 downto 0),
y (2 downto 0) => f (45 downto 43)
);
acc46_7: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => f (45 downto 0),
b (45 downto 0) => h (45 downto 0),
y (45 downto 2) => g (43 downto 0),
y (1 downto 0) => g (45 downto 44)
);
acc46_8: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => g (45 downto 0),
b (45 downto 0) => i (45 downto 0),
y (45 downto 1) => h (44 downto 0),
y(0) => h(45)
);
acc46_9: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => h (45 downto 0),
b (45 downto 0) => j (45 downto 0),
y (45 downto 0) => i (45 downto 0)
);
acc46_10: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => i (45 downto 0),
b (45 downto 0) => k (45 downto 0),
y (45 downto 1) => j (44 downto 0),
y(0) => j(45)
);
acc46_11: acc46
port map (
clkenb => clkenb,
sysclk => sysclk,
gblreset => gblreset,
a (45 downto 0) => g (45 downto 0),
b (45 downto 0) => j (45 downto 0),
y (45 downto 2) => k (43 downto 0),
y (1 downto 0) => k (45 downto 44)
);
end;