---

sample.top

---

#module     "sample";
#part_type "4013E";
#family "XC4000";
#package "PQ240";
#speed "-3";

#directory "work";
#include    "sample.pin";
#insert_upcase "startup.vhd",connections="startup_blk.conn";
#insert "rstbuff.vhd";

#insert "accblock.top",connections="block1.conn";
#insert "accblock.vhd",connections="block2.conn";
#insert "cmp46.vhd",connections="cmpfull.conn";


#insert "bufgs.vhd",connections="clkenb_a.conn";
#insert "bufgs.vhd",connections="clkenb_b.conn";
#clock      "sysclk_pin"      40;
#dont_touch "startup_1";
#dont_touch "bufgs_1";
#dont_touch "bufgs_2";
#black_box "startup";
#black_box "bufgs";

---

HDLMaker Generated Files

sample.v	Verilog file
sample.job	Synopsys script file
sample.prj	Synplicity Project file
sample.ucf	Xilinx constraint file
sample.Make	Synopsy Make file
sample_v.cmd	Leapfrog Make file
sample_mt.do	Model Tech script file
sample_batch.Make	Synopsis batch Make file
sample.errors	DRC Error file

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