pintest_ctrl.job
TOP = pintest_ctrl
PART = "xcv800fg680-5"
read -format verilog pintest_ctrl.v
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > pintest_ctrl.fpga
report_timing > pintest_ctrl.timing
write -format db -hierarchy -output pintest_ctrl.db
exit