SRL16E.job
TOP = SRL16E
PART = "xcv800fg680-5"
read -format verilog SRL16E.v
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > SRL16E.fpga
report_timing > SRL16E.timing
write -format db -hierarchy -output SRL16E.db
exit