RAMB4_S1_S16.job
TOP = RAMB4_S1_S16
PART = "xcv800fg680-5"
read -format verilog RAMB4_S1_S16.v
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > RAMB4_S1_S16.fpga
report_timing > RAMB4_S1_S16.timing
write -format db -hierarchy -output RAMB4_S1_S16.db
exit