FDCE.job
TOP = FDCE
PART = "xcv800fg680-5"
read -format verilog FDCE.v
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > FDCE.fpga
report_timing > FDCE.timing
write -format db -hierarchy -output FDCE.db
exit
HDLMaker Generated Files