CLKDLL.job
TOP = CLKDLL
PART = "xcv800fg680-5"
company = "Polybus Systems Corp, Westford MA"
read -format verilog CLKDLL.v
uniquify
current_design TOP
remove_constraint -all
compile -map_effort high
report_fpga > CLKDLL.fpga
report_timing > CLKDLL.timing
write -format db -hierarchy -output CLKDLL.db
exit