HDLmaker

<body topmargin=0 leftmargin=0 marginheight=0 marginwidth=0> <table cellpadding=0 cellspacing=0 border=0><tr> <td valign="top" colspan=2 height=90 BGCOLOR="#CC9900" TEXT="#080000" bgproperties="fixed" background="045005a0dwnjzk.gif"> <div> <B>HDLmaker</B></div> <bR> <div> </div> </td> </tr><tr> <td valign="top" width=210 BGCOLOR="#FFFFFF" TEXT="#080000"> <bR> <div> <B><IMG SRC="05c69830.gif" border=0 width="105" height="131" ALIGN="BOTTOM" HSPACE="0" VSPACE="0"></B><A HREF="http://www.polybus.com" TARGET="_top" TITLE="http://www.polybus.com"><U><B>Polybus Systems Corp.</B></U></A></div> <bR> <div> <B>contact: </B><A HREF="mailto:bjrosen@polybus.com" TARGET="_top" TITLE="mailto:bjrosen@polybus.com"><U><B>bjrosen@polybus.com</B></U></A><B> </B></div> <div> <B>     Resume: </B><A HREF="http://www.polybus.com/hdlmaker/Resume.html" TARGET="_top" TITLE="http://www.polybus.com/hdlmaker/Resume.h"><U><B>Joshua Rosen</B></U></A></div> <bR> <div> <A HREF="index_m.htm#platforms" TARGET="TRLX_Middle" TITLE="HDLmaker"><U><B>Platforms</B></U></A></div> <div> <A HREF="index_m.htm#features" TARGET="TRLX_Middle" TITLE="HDLmaker"><U><B>Features</B></U></A></div> <div> <A HREF="index_m.htm#portability_" TARGET="TRLX_Middle" TITLE="HDLmaker"><U><B>Portability</B></U></A></div> <div> <A HREF="index_m.htm#it_s_free_" TARGET="TRLX_Middle" TITLE="HDLmaker"><U><B>It's Free</B></U></A></div> <div> <A HREF="index_m.htm#whats_new" TARGET="TRLX_Middle" TITLE="HDLmaker"><U><B>What's New</B></U></A></div> <div> <A HREF="index_m.htm#services__not_free_" TARGET="TRLX_Middle" TITLE="HDLmaker"><U><B>Services</B></U></A></div> <div> <A HREF="index_m.htm#customization_" TARGET="TRLX_Middle" TITLE="HDLmaker"><U><B>Customization</B></U></A></div> <div> <A HREF="index_m.htm#infiniband_link_layer_and_transport" TARGET="TRLX_Middle" TITLE="HDLmaker"><U><B>InfiniBand Link Layer and Transport</B></U></A></div> <div> <A HREF="http://www.polybus.com/xilinx_test_patterns" TARGET="_top" TITLE="http://www.polybus.com/xilinx_test_patte"><U><B>Xilinx Test Patterns</B></U></A></div> <div> <A HREF="http://www.polybus.com/xilinx_on_linux.html" TARGET="_top" TITLE="http://www.polybus.com/xilinx_on_linux.h"><U><B>Xilinx on Linux</B></U></A><A HREF="http://www.polybus.com/xilinx_on_linux.html" TARGET="_top" TITLE="http://www.polybus.com/xilinx_on_linux.h"><U><B> Howto</B></U></A></div> </td> <td valign="top" height=390 BGCOLOR="#FFFFFF" TEXT="#080000"> <bR> <div> <A HREF="id17.htm" TARGET="_top" TITLE="Download Installation"><U>Download & Installation</U></A>   |   <A HREF="id18.htm" TARGET="_top" TITLE="Running HDLmaker"><U>Running HDLmaker</U></A>   |   <A HREF="id20.htm" TARGET="_top" TITLE="Users Manual"><U>Users Manual</U></A>   |   <A HREF="id27.htm" TARGET="_top" TITLE="License"><U>License</U></A>   |   <A HREF="id19.htm" TARGET="_top" TITLE="Contact Us"><U>Contact Us</U></A>   |   <A HREF="id31.htm" TARGET="_top" TITLE="Help"><U>Help</U></A></div> <bR> <div> <B>HDLmaker is offered free of charge by Polybus Systems corporation under a BSD style open source </B><A HREF="id27.htm" TARGET="_top" TITLE="License"><U><B>license.</B></U></A><B>  </B></div> <div> <B>Polybus offers Intellectual Property including InfiniBand Link Layer and Transport Layer cores, and a comprehensive set of In System FPGA test patterns. Polybus also provides FPGA and ASIC design services.</B></div> <div> <B>Polybus is the leading supplier of InfiniBand cores for use in Xilinx Virtex2P, Xilinx Virtex4FX, Xilinx Virtex5, Xilinx Virtex6, Altera Stratix2GX and Stratix4GX and GT FPGAs as well for ASICs. We offer an IBA Release 1.1 compliant Link Layer core (10GBit/Second), an IBA Release 1.2 compatible Double Data Rate Link Layer core (20GBit/Second) , a 4X QDR Link Layer Core (40GBits/Second) for the Stratix4GT and the Virtex6HXT and an 8X QDR Link Layer Core (80 Gbits/Second) of ASICs. SDR and DDR InfiniBand Target Channel Adapters are available for both Altera and Xilinx FPGAs. For more information see,</B></div> <div> <A HREF="http://www.polybus.com/ib_link_layer_website" TARGET="_top" TITLE="http://www.polybus.com/ib_link_layer_web"><U>http://www.polybus.com/ib_link_layer_website</U></A>.</div> <bR> <div> <B>If you are looking for FPGA or ASIC design consulting or would like more information about our cores please contact Joshua Rosen </B><A HREF="mailto:bjrosen@polybus.com" TARGET="_top" TITLE="mailto:bjrosen@polybus.com"><U><B>bjrosen@polybus.com</B></U></A><B>, (978) 828-0944.</B></div> <bR> <div> <B>HDLmaker may be downloaded </B><A HREF="id17.htm" TARGET="_top" TITLE="Download Installation"><U><B>here</B></U></A><B>.</B></div> <bR> <div> HDLmaker is a tool for generating Verilog designs. HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks:</div> <bR> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Writes hierarchical Verilog code </div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Generates retargetable IO pad rings </div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Generates all of the necessary scripts and Make files </div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Supports mulitlanguage projects</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Designs are portable between FPGA families and CAE tools</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Simplifies the reuse of HDL code </div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Converts HDLmaker, Verilog and VHDL files into fully hyper linked HTML</div> <bR> <bR> <div> The designer writes the leaf cells and defines the pins, HDLmaker does the rest. </div> <bR> <div> <B> <A NAME="platforms"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Platforms</B></div> <div> HDLmaker is an open source program that runs on any Linux/UNIX. HDLmaker has been tested on  Sun OS, Solaris, HP, Linux and SGI systems. </div> <bR> <div> HDLmaker also runs under the Cygwin environment on Windows. Cygwin is available from <A HREF="http://www.cygwin.com" TARGET="_top" TITLE="http://www.cygwin.com"><U>http://www.cygwin.com</U></A>.</div> <bR> <div> <B> <A NAME="features"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Features</B></div> <div> Writes Hierarchical Verilog.</div> <bR> <div> Output can be targeted to either Verilog or VHDL (VHDL support has been deprecated). </div> <bR> <div> Supports mixed language development.</div> <bR> <div> Generates PC board netlists in both PADS PCB and SCALD formats. </div> <bR> <div> Generates Schematics in Postscript format. </div> <bR> <div> Supports the most popular FPGAs </div> <div> Xilinx Virtex6,Virtex5,Virtex4,Virtex2P, Virtex2,VirtexE,Virtex, Spartan3, Spartan2,4000E,4000EX,4000XL,5200,9500, Altera Stratix ,Stratix2GX,Stratix4GX,Stratix4GT</div> <bR> <div> Supports the most popular synthesizers </div> <div> Synplify</div> <div> Xilinx XST</div> <div> Altera Quartus</div> <div> Synopsys Design Compiler</div> <div> Precision</div> <bR> <div> Supports most simulators </div> <div> Cadence Verilog XL</div> <div> Cadence NC-SIM</div> <div> Mentor Questa and ModelSim</div> <div> Synopsys VCS</div> <bR> <div> HTML Generation</div> <div> HDLmaker generates an HTML version of the design with hyper links from all source files to generated files and from all component instances to the component's module. Verilog and VHDL HTMLized are also syntax colored.</div> <bR> <div> <B> <A NAME="portability_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Portability </B></div> <div> HDLmaker based designs can be easily retargeted to different FPGA or ASIC families, tools and languages, usually with a simple command line switch or with a single line in a source file. </div> <bR> <div> Any supported synthesizer or simulator can be used without any additional work on the part of the user. </div> <bR> <div> <B> <A NAME="it_s_free_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>It's Free </B></div> <div> HDLmaker may be used by individuals and corporations for the design and development of FPGAs and ASICs at no charge. HDLMaker is available under a BSD style <A HREF="id27.htm" TARGET="_top" TITLE="License"><U>license</U></A>.</div> <bR> <div> <B> <A NAME="whats_new"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>What's New</B></div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Added #code, #parameter</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Improved #define</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Added Virtex5 support</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Added more support for Stratix2 and Stratix2GX</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Added support for Virtex2ProX, Spartan3e and Stratix2GX</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Creates Makefiles for ModelSim</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">More Virtex4 support</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Added frczero to the .pin file</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">insert_compare, Inserts a module with a compare wrapper around it</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Added HDLMAKER_ALLOW_SUB variable</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Added xst_directive</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Floorplanning support for Multipliers and Block RAMs</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">New XST constraints</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Improved DDR IO support including differential DDR</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Improved Xilinx project support</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex4 Support</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Better ModelSim support. Creates three command files, foo_compile_mt.cmd to compile the modules, foo_i_mt.cmd for interactive use, and foo_batch_mt.cmd for batch simulation.</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Initial values of HDLmaker variables can be passed in from the command line or from a file</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Better comment support</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">More flexible #clock statement</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Comments in pin files</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Support for Xilinx ISE 6.1</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Support for Virtex2P</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Support for Precision and ModelSim added</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Large Project Support, HDLMaker now operates across multiple directories</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Virtex2, Spartan2 and Spartan2E support added</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Altera Stratix support added</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Multilanguage project support. Can embed VHDL entities into Verilog files and Verilog modules into VHDL files</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Altera Stratix4GX and GT</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Xilinx Virtex6</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Support for Quartus II 9.1 and ISE 11</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Support for Acronix Speedster FPGAs</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Support for Verilog 2001 port definitions</div> <div> <IMG BORDER="0" SRC="Symb075c00b700f000000000.gif" HEIGHT="16" WIDTH="24" ALIGN="bottom" HSPACE="0" VSPACE="0">Added -tree_copy and -src_copy switches which generate export scripts</div> <bR> <div> <B> <A NAME="services__not_free_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Services (Not free)</B></div> <div> FPGA and ASIC design</div> <bR> <div> <B> <A NAME="infiniband_link_layer_and_transport"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><A HREF="http://www.polybus.com/ib_link_layer_website/" TARGET="_top" TITLE="http://www.polybus.com/ib_link_layer_web"><U><B>InfiniBand Link Layer and Transport Layer Cores (Not Free)</B></U></A></div> <div> An IBA Release 1.1 compliant 4X/1X InfiniBand Link Layer Core and a companion Transport Layer Core. The Link Layer Core operates at 4X speeds with minimal latency and is suitable for use in both Xilinx Virtex 2P FPGAs and ASICs. A highly customizable companion Transport Layer Core is also available which is suitably for a range of Target Channel Applications.</div> <bR> <div> <B> <A NAME="xilinx_test_patterns__not_free_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><A HREF="http://www.polybus.com/xilinx_test_patterns" TARGET="_top" TITLE="http://www.polybus.com/xilinx_test_patte"><U><B>Xilinx Test Patterns (Not Free)</B></U></A></div> <div> A customizable set of FPGA test patterns for all Xilinx FPGAs. The suite consists of over 400 patterns which test the internal functionality and interconnect of any Xilinx FPGA. The tests help eliminate FPGAs that have failed due to handling problems and infant mortality. In addition the patterns provided a greatly enhanced level of testing which helps assure the future upgradability of FPGA based systems.</div> <bR> <div> <B> <A NAME="customization_"><IMG BORDER="0" SRC="1x1.gif" HEIGHT="1" ALIGN="bottom" WIDTH="1" HSPACE="0" VSPACE="0" ></A></B><B>Customization (Not Free)</B></div> <div> Polybus will customize HDLmaker for your environment: Add conversions between any netlist format and either VHDL or Verilog including any custom attributes that are specific to your company. </div> <bR> <div> Add support for other simulators and synthesis tools </div> <bR> <div> Provide glue between different CAE tools. </div> </td> </tr></table></body>