module sample(

cclk_pin,
din_pin,
done_pin,
dout_pin,
gblreset_pin,
init_l_pin,
mclk_pin,
probe_pin,
prog_l_pin,
sysclk_pin,
tclk_pin,
tdi_pin,
tdo_pin,
tms_pin

);
// IO Declarations
input [9:1] mclk_pin;
output [1:0] probe_pin;
input sysclk_pin;

// Signal Declarations

wire [45:0] a;
wire [45:0] b;
wire [1:0] clkenb;
wire gblreset;
wire [9:1] mclk;
wire [1:0] probe;
wire sysclk;





// Component Instance sample_pads_1
sample_pads sample_pads_1(

.mclk_pin({mclk_pin[9:1]}),
.probe({probe[1:0]}),
.sysclk_pin(sysclk_pin),
.mclk({mclk[9:1]}),
.probe_pin({probe_pin[1:0]}),
.sysclk(sysclk)

);

// Component Instance accblock_1
accblock accblock_1(

.clkenb(clkenb[0]),
.gblreset(gblreset),
.sysclk(sysclk),
.a({a[45:0]})

);

// Component Instance accblock_2
accblock accblock_2(

.clkenb(clkenb[1]),
.gblreset(gblreset),
.sysclk(sysclk),
.a({b[45:0]})

);
endmodule