HDLmaker

HDLmaker was written by Joshua Rosen and Polybus Systems Corp, as an aid for the development of complex FPGA designs. It is offered free of charge, without warranty either expressed or implied. All comments, complaints or suggestions should be sent to bjrosen@polybus.com.

HDLmaker is an open source program. HDLmaker source code is included in the release. You are free to modify it and use it for your own purposes, however you may not include any HDLmaker source code in any commercial product without receiving written consent from Polybus Systems Corp. If you are interested licensing HDLmaker in whole or in part please contact us at bjrosen@polybus.com.

Polybus offers extensive hardware and software development services. For more information please contact bjrosen@polybus.com, or call (978)692-4828.

Index

Overview

HDLmaker is a tool for generating VHDL and Verilog FPGA designs. HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks:

Writes all of the hierarchical code
Generates retargetable IO pad rings
Generates all of the necessary scripts and Make files
Converts from ABEL to VHDL and Verilog
Converts PCB net lists into VHDL and Verilog
Generates SCALD and PADS pc board netlists
Generates Schematics in Postscript format
Designs are portable between FPGA families and CAE tools
Simplifies the reuse of HDL code
The designer writes the leaf cells and defines the pins, HDLmaker does the rest.

Features

Available for Sun OS, Solaris, HP and Linux
Writes VHDL and Verilog

Output can be targeted to either VHDL or Verilog.

Generates PC board netlists in both PADS PCB and SCALD formats.
Generates Schematics in Postscript format.
Supports the most popular FPGAs

Xilinx Virtex,VirtexE,4000E,4000EX,4000XL,5200,9500

Lucent ORCA 2C

Supports the most popular synthesizers

Synplify

Synopsys FPGA Compiler

Exemplar

Supports several simulators

Fintronics Finsim

Cadence Leapfrog

Cadence Verilog XL

Model Technologies (VHDL and Verilog)

Converts ABEL to VHDL
Converts VHDL to Verilog (Simple VHDL only, resulting code may need some hand modifications)
Self Documenting

HDLmaker generates an HTML version of the design with hyperlinks from all source files to generated files and from all component instances to the component's module.

Portability

HDLmaker based designs can be easily retargeted to different FPGA families, tools and languages, usually with a simple command line switch or with a single line in a source file.

Any supported synthesizer or simulator can be used without any additional work on the part of the user. HDLmaker generates all required Makefiles and Scripts automatically.

Board level simulation

Translates PADS PCB files into VHDL.

Translates Scald Netlists into Verilog or VHDL

It's Free
HDLmaker may be used by individuals and corporations for the design and development of FPGAs and ASICs at no charge. You may also modify the code for in house use, if you would like your modifications included in the main release of HDLmaker please send them to us. Support for HDLmaker is not free, if you would like any features added please contact us and we will be happy to quote you a price.
You may not sell HDLmaker or any derivative software product (i.e. a program containing any HDLmaker source code) without express written consent from Polybus Systems Corp. If you are interested in producing a commercial product based on HDLmaker, please contact us about licensing.

Services (Not free)

FPGA design and Verification

Polybus designs complex FPGAs in either VHDL or Verilog (your choice)

Customization

Polybus will customize HDLmaker to your environment:

Add conversions between any netlist format and either VHDL or Verilog including any custom attributes that are specific to your company.

Add support for other simulators and synthesis tools

Provide glue between different CAE tools.

contact: bjrosen@polybus.com
Resume: Joshua Rosen

Download Software (Includes all libraries, Linux Versions)

HDLmaker Version 5.6.0 (01/11/2001)

Installing Software

Untar it, then run the install script which will compile hdlmaker for your architecture.

tar -xvf hdlmaker_install.tar
cd hdlmaker_install
./install.csh

Examples:

Getting Started

Decompress and untar hdlmaker_lib
Execute hdlmaker/install.csh
Add the HDLMAKER_LIB environment value to your .cshrc file. HDLMAKER_LIB specifies the path the hdlmaker_lib directory:

setenv HDLMAKER_LIB {/home/polybus/hdlmaker_lib}

Add a default FPGA family environment variable to your .cshrc

if ( ! $?FPGA_FAMILY ) then

setenv FPGA_FAMILY virtex

endif

The supported FPGA_FAMILYs are
xc4000e
xc4000ex
xc4000xl
xc5200
orca2ca
virtex

Add the FPGA_NOXBLOX environment variable. The FPGA_NOXBLOX variable is used to turn off XBLOX and LOGIBLOX synthesys when using Synopsys FPGA compiler. I have found that the use of XBLOX and LOGIBLOX can make a design unroutable.

if ( ! $?FPGA_NOXBLOX ) then

setenv FPGA_NOXBLOX TRUE

endif

Source the following files in your .cshrc

source $HDLMAKER_LIB/csh/hdlmaker.cshrc

To get help

hdlmaker -help all

To grab a sample design

hdlmaker sample.top

Library Search Paths

HDLmaker uses an optional file to specify the file search order. The file (called polybus.lib) must be placed in the local design directory.

Directories are searched in order starting with the local directory, followed by the directories in polybus.lib, and then the HDLmaker standard libraries.

The format of a polybus.lib entry is:

#design "library_name" "path"

Example polybus.lib

Using HDLmaker

HDLmaker has two major file types, these are:

Recompiling HDLmaker

Hdlmaker is supported on Linux, Solaris, and HP. To recompile it for any of these platforms, do the following:

cd $HDLMAKER_LIB/sources/hdlmaker_sources

make install

Other Links

Xilinx on Linux HOWTO

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