Environment variables

In your .cshrc you must specify four environment variables.

HDLMAKER_LIB Specifies the path to hdlmaker's library

HDLMAKER_MACHINE Specifies the Machine used for the synthesis batch queue

If there is no batch queue then either don't set this

variable or set it to 0

HDLMAKER_FAMILY Specifies the FPGA family, legal values are

xc4000e

xc4000ex

xc5200

orca2ca

HDLMAKER_SYNTHESYS Specifies the synthesys tool, legal values are

synopsys

synplicity

fpgaexpress

exemplar

HDLMAKER_BATCH_Q Specifies the synthesys batch queue script name. If there is

no batch queue then set this variable to the systhesis program name.

For example if you are running synopsys use:

setenv HDLMAKER_BATCH_Q {"dc_shell - f"}

HDLMAKER_SYNTHESYS_EXTENSION Specifies the file extension of the command script. For the

batch system this variable may be left undefined or set to 0. If

dc_shell is being used this variable must be set to .job.

setenv HDLMAKER_SYNTHESYS_EXTENSION {.job}

HDLMAKER_LANGUAGE Specifies hdlmaker's output language, the default is VHDL.

setenv HDLMAKER_LANGUAGE verilog

setenv HDLMAKER_LANGUAGE vhdl

HDLMAKER_VERILOG_CMD Specifies the verilog command used in the verilog script.

setenv HDLMAKER_VERILOG_CMD "virsim verilog-vw"

setenv HDLMAKER_LIB {/usr/local/lib/hdlmaker}

setenv HDLMAKER_MACHINE {goffin}

setenv HDLMAKER_FAMILY {xc4000e}

setenv HDLMAKER_SYNTHESYS {synplicity}

setenv HDLMAKER_BATCH_Q {s3fpga2job_q}